Error-Correcting Codes

(A) Error-correcting schemes for wireless communication systems

In the next-generation mobile communications and Internet of Things, high error-correction capability, low computational complexity, and efficient memory management are required, and various error-correcting schemes have been studied to satisfy these requirements such as low density parity check (LDPC) codes, spatially coupled LDPC (SC-LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH codes), and polar codes.

Upper bounds and simulated block error probabilities of uniform-quantized successive cancellation (SC) decoding and nonuniform-quantized SC decoding for polar codes over AWGN channel
Frame error rate according to decoding scheme of quasi-cyclic SC-LDPC code

(B) Error-correcting schemes for memories such as NAND flash memory and DRAM

In memory systems (e.g., NAND flash memory and DRAM) to which an ultra-fine process of 10 nm or less is applied, problems that degrade data reliability are caused due to many errors that occur due to rapid deterioration of channels. To solve this problem, it is necessary to research the application of error correction techniques to efficiently control errors in memory systems. In this study, we research various error correction techniques with low complexity and high reliability for the next-generation memory systems.

  • Channel modeling and analysis for various errors

NAND flash chip contains several planes and each plane consists of a set of blocks. A block has many pages and each page consists of many memory cells. Therefore, cell is a basic storage unit of NAND flash memory. The threshold voltage of a cell is quantized into multiple discrete levels to represent data. For MLC NAND flash memory, the left bit and the right bit of two bits are called as the most significant bit and the least significant bit, respectively.

Approximated Gaussian distributions of cell threshold voltages in an MLC NAND flash memory

F. Sun, K. Rose, and T. Zhang, "On the use of strong BCH codes for improving multilevel NAND flash memory storage capacity,'' 2006 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, vol. 15, no. 8, pp. 860-862, Aug. 2011.

To represent the possible fault modes that may occur in current/future DRAM systems, error model is first described. This model covers various type of faults that arise in DRAM devices, data-bus and address-bus. Faults in DRAM subsystems are caused due to a variety of sources such as cosmic rays, circuit failure, and signal integrity.

Various faults and the corresponding error models

Yeleswarapu R, Somani AK. 2021. Addressing multiple bit/symbol errors in DRAM subsystem. PeerJ Computer Science 7: e359 https://doi.org/10.7717/peerj-cs.359

  • Error-correcting schemes for memory systems

In memory systems, various error-correcting codes are applied such as BCH codes, LDPC codes, polar codes, chipkill, single device data correction (SDDC), and single-bit error correction and double-bit error detection (SECDED) code according to the requirements for code design.

Encoding scheme of CRC and even parity bits for SDDC

(C) Blind detection/identification of error-correcting codes in a non-cooperative context

Error-correcting codes (ECCs) are essential to improve the reliability of digital communication systems. ECCs can detect or correct the errors by introducing and utilizing the systematic parity check bits. However, ECCs deteriorate the spectral efficiency of digital communication systems and hence it is always preferable to enhance the spectral efficiency by any means. In order to enhance the spectral efficiency, the blind detection/identification schemes of ECCs have been actively studied.

Soonhee Kwon and Dong-Joon Shin, "Blind Classification of Error-Correcting Codes for Enhancing Spectral Efficiency of Wireless Networks," IEEE Transactions on Broadcasting, Accepted.
Minki Song and Dong-Joon Shin, "Asymptotic Analysis of Blind Reconstruction of BCH Codes Based on Consecutive Roots of Generator Polynomials." IEEE Access, vol. 8, pp. 206514-206526, Nov. 2020.
Soonhee Kwon and Dong-Joon Shin, "Analysis of Blind Reconstruction of BCH Codes," Entropy, Vol. 22, No. 11, pp. 1-16, Nov. 2020.
Daemin Jo, Soonhee Kwon, and Dong-Joon Shin, "Blind Reconstruction of BCH Codes Based on Consecutive Roots of Generator Polynomials," IEEE Communications Letters, Vol. 22, No. 5, pp. 894-897, Feb. 2018.